JPH0412035B2 - - Google Patents
Info
- Publication number
- JPH0412035B2 JPH0412035B2 JP57004423A JP442382A JPH0412035B2 JP H0412035 B2 JPH0412035 B2 JP H0412035B2 JP 57004423 A JP57004423 A JP 57004423A JP 442382 A JP442382 A JP 442382A JP H0412035 B2 JPH0412035 B2 JP H0412035B2
- Authority
- JP
- Japan
- Prior art keywords
- metal mesh
- chip
- semiconductor device
- tape
- ground terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57004423A JPS58122776A (ja) | 1982-01-14 | 1982-01-14 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57004423A JPS58122776A (ja) | 1982-01-14 | 1982-01-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58122776A JPS58122776A (ja) | 1983-07-21 |
JPH0412035B2 true JPH0412035B2 (en]) | 1992-03-03 |
Family
ID=11583852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57004423A Granted JPS58122776A (ja) | 1982-01-14 | 1982-01-14 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58122776A (en]) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5411896A (en) * | 1992-03-16 | 1995-05-02 | Delco Electronics Corporation | Method of making supra-passivant grid |
US5399902A (en) * | 1993-03-04 | 1995-03-21 | International Business Machines Corporation | Semiconductor chip packaging structure including a ground plane |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5627962A (en) * | 1979-08-15 | 1981-03-18 | Matsushita Electric Ind Co Ltd | Integrated circuit device |
JPS5636157A (en) * | 1979-08-31 | 1981-04-09 | Hitachi Ltd | Semiconductor device |
-
1982
- 1982-01-14 JP JP57004423A patent/JPS58122776A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58122776A (ja) | 1983-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5436203A (en) | Shielded liquid encapsulated semiconductor device and method for making the same | |
EP0682812B1 (en) | Thermally conductive integrated circuit package with radio frequency shielding | |
JP2002524858A (ja) | 電磁干渉シールド装置及び方法 | |
TWI605564B (zh) | 封裝結構及其製法 | |
US10553954B2 (en) | Wireless device | |
JPS5992556A (ja) | 半導体装置 | |
US6430059B1 (en) | Integrated circuit package substrate integrating with decoupling capacitor | |
US20050046046A1 (en) | Semiconductor package structure and method for manufacturing the same | |
KR100698570B1 (ko) | 전자파 간섭을 감소시키는 패키지 디바이스 | |
TW201214650A (en) | Chip package having fully covering shield connected to GND ball | |
JPH0412035B2 (en]) | ||
JP3234666B2 (ja) | 半導体集積回路装置 | |
JPH044753B2 (en]) | ||
US20020066592A1 (en) | Ball grid array package capable of increasing heat-spreading effect and preventing electromagnetic interference | |
CN111081696B (zh) | 半导体封装和制造半导体封装的方法 | |
CN211238248U (zh) | 半导体封装 | |
US7838777B2 (en) | Signal transmission structure, package structure and bonding method thereof | |
JPH1140709A (ja) | 半導体実装構造およびその製造方法 | |
WO2019207657A1 (ja) | 半導体装置および半導体装置の製造方法 | |
JP3296168B2 (ja) | 半導体装置 | |
JP2630294B2 (ja) | 混成集積回路装置およびその製造方法 | |
JPS607741A (ja) | 混成集積回路装置 | |
JPH08255811A (ja) | 電子部品の接続装置 | |
JP2867710B2 (ja) | プラスチック・ピン・グリッド・アレイ | |
CN101090079A (zh) | 防止芯片被干扰的封装方法及其封装结构 |